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Article · Bulletin of the National Engineering Academy of the Republic of Kazakhstan · December 15, 2021

Implementation of a number recognition algorithm built using a neural network on the BASYS3 FPGA panel

Aksultan Mukhanbet, E. S. Nurakhov, Beimbet Daribayev

Aksultan Mukhanbet
Open via DOIPDFDOI 10.47533/2020.1606-146x.119

Abstract

In recent years, some field programmable valve arrays (FPGAs) based on CNN release phase accelerators have been introduced. FPGA is widely used in portable devices. They can be programmed to achieve higher concurrency and provide better performance. The power consumption of the FPGA is lower than that of GPUs with the same workload. These reasons make the FPGA suitable for implementing the CNN release phase. They can provide relative output performance for GPUs and achieve low power consumption, which is very important for portable devices. To effectively implement the CNN output phase on the FPGA, the design should have high parallelism, and the hardware resources used should be minimized to reduce the area and power consumption. In the process of working with the help of a neural network, an algorithm for recognizing handwritten numbers is implemented. A special architecture is being created to implement a neural network at the appatent level. The performance during operation and power consumption is comparable to the performance of the processor and the GPU.

Embedded Systems Design TechniquesAdvanced Neural Network ApplicationsEmbedded Systems and FPGA Applicationshandwritten digit recognitionFPGA implementationneural network hardware

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