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Talk · International Conference on Telecommunications and Signal Processing · July 1, 2019

Hardware Implementation of Video Processing Device using Residue Number System

Dmitrii Kaplun, Nikolay Ivanovich Chervyakov, Pavel Alekseyevich Lyakhov, Andrey S. Ionisyan, Maria Vasilyevna Valueva, Vyacheslav V. Gulvanskiy

Dmitry Kaplun
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Abstract

This paper considers the creation of video signal processing device. Important performance criteria of these devices are speed and power consumption. We used an Alinx AX309 board containing FPGA Xilinx Spartan6-xc6s1x9 as a hardware basis for the implementation of the system. OV7670 video camera was used to obtain a video signal. The output of the processed video was carried out on the Alinx AN430 LCD display and on the standard VGA port. We used the Residue Number System to accelerate calculations. It allowed to improve device speed by 28% compared to using traditional two's complement number system.

Embedded Systems and FPGA ApplicationsCryptography and Residue ArithmeticEmbedded Systems Design Techniquesresidue number systemvideo signal processingFPGA implementation

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