Talk · IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering · January 26, 2021
Development and Implementation of the H.264-Codec Deblocking Filter Based on the MIPS SIMD Architecture
Danil V. Bogaevskiy, Maxim V. Minenko, Sergey Ezhov, Dmitrii Kaplun
Abstract
The paper presents the approach to a virtual architecture system profiling within a QEMU emulator. The aim of the research is to demonstrate virtual architecture MIPS64 Release 6 profiling within QEMU emulator taking as an example implementation of the H.264 video codec element, namely, a deblocking filter. The described approach is characterized by the ability to test any guest models of vector processors. We present the model of vector processor based on the MIPS SIMD Architecture (MSA) and the recommendations on vectorization optimization based on metrics for vectorization performance estimation that are suggested in the paper. The approach and special program tool for metrics estimation were developed by the authors. It is shown through emulation that the model based on the MSA will give better performance for image and video processing tasks like elements of the H.264 video codec.
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